1. Field of the Invention
Generally, the present disclosure relates to the manufacture of FET semiconductor devices, and, more specifically, to a tunneling field effect transistor (TFET) and various methods of making such a transistor.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout. So-called metal oxide field effect transistors (MOSFETs or FETs) represent one important type of circuit element that substantially determines performance of the integrated circuits. Field effect transistors can be made in a variety of different configurations, e.g., planar devices, 3D devices such as FinFETs, nanowire devices, etc. Irrespective of the configuration of the transistor device, a FET typically includes a source region, a drain region, a channel region that is positioned between the source region and the drain region, and a gate electrode positioned above or around the channel region. Drive current through the FET is controlled by setting the voltage applied to the gate electrode. For example, for an NMOS device, if there is no voltage applied to the gate electrode, then there is no current flow through the NMOS device (ignoring undesirable leakage currents, which are relatively small). However, when an appropriate positive voltage is applied to the gate electrode, the channel region of the NMOS device becomes conductive, and electrical current is stimulated to flow between the source region and the drain region through the conductive channel region.
A planar FET is typically formed in and above an active region having a planar upper surface. In contrast to a planar FET, there are so-called 3D devices, such as an illustrative FinFET device, which is a three-dimensional structure. FIG. 1A is a perspective view of an illustrative prior art FinFET semiconductor device 10 that is formed above a semiconductor substrate 12 that will be referenced so as to explain, at a very high level, some basic features of a FinFET device. In this example, the FinFET device 10 includes a plurality of trenches 14 that define three illustrative fins 16, a gate structure 18, sidewall spacers 20 and a gate cap layer 22. The fins 16 have a three-dimensional configuration: a height H, a width W and an axial length L. The axial length L of the fins 16 corresponds to the direction of current travel in the device 10 when it is operational. The portions of the fins 16 covered by the gate structure 18 are the channel regions of the FinFET device 10. The gate structure 18 is typically comprised of a layer of gate insulating material, e.g., a layer of high-k insulating material (k-value of 10 or greater) or silicon dioxide, and one or more conductive material layers (e.g., metal, metal alloy, metal stack and/or polysilicon) that serve as the gate electrode for the device 10.
So-called tunneling field effect transistors (TFETs) are being investigated for being used in manufacturing current-day and advanced generation integrated circuit products. Relative to traditional planar and 3-D transistor devices, TFETs tend to exhibit generally much faster switching speeds, but they have major issues with the generation of sufficiently high on-state currents (Ion). FIG. 1B is a schematic depiction of an illustrative point-tunneling FET 10P. As depicted, the device 10P is comprised of a P-doped source region 12, an N-doped drain region 14 and a channel or intrinsic region 16. The channel region 16 is typically un-doped. Also depicted are a gate insulation layer 18 and a gate electrode 20. For a point-tunneling device like device 10P, the gate electrode 20 will typically overhang the source region 12 by a distance 22 that may range from about 0-1 nm. In general, as noted above, an appropriate control voltage must be applied to the gate electrode 20 of the device 10P to establish a conductive channel whereby current may flow from the source region 12 to the drain region 14. In an ideal situation, changing a field effect transistor from an OFF-state condition to an ON-state condition would occur instantaneously and simultaneously across the entire channel length of the device. However, in a real-world device, such a conductive channel region does not form instantaneously. Rather, the conductive channel forms over a finite time period, albeit a very small time period, as the voltage is being applied to the gate electrode. It is only after a period of time that the full ON-state current of the device flows through the channel region of the device. Accordingly, FIG. 1B depicts the device 10P at a point in time where current, generally referenced with the number 24, has just started to flow in the channel region 16. More specifically, three schematically depicted lines of current 24A-24C are depicted in FIG. 1B. The current flow 24 begins with current 24A, followed by 24B, followed by 24C, etc. This process continues until such time as the device 10P is fully turned ON, and the maximum drive current 24 flows through the channel region to the drain 14.
FIG. 1C is a schematic depiction of another form of a TFET device with a different architecture—a so-called line-tunneling FET 10L. The line-tunneling FET 10L has the same basic configuration as the device 10P, except that the gate electrode 20 is positioned above the P-doped source region 12 by a distance 26 that may range from about 5-15 nm. In a line-tunneling FET 10L, while there are still point-tunneling current 24 contributions, there are mainly line-tunneling currents 28 that tunnel substantially vertically toward the gate electrode 20 in the source region and then flow toward the channel.
FIG. 1D is a graph depicting modeling results for illustrative all silicon TFET devices. More specifically, the horizontal axis is the voltage between the gate and source (Vgs) while the vertical axis is the current (Ids) that flows through the channel region. As noted above, the conductive channel region of a real-world transistor device takes some time before it is fully formed and thus before the device is completely turned ON. Device designers use a term—sub-threshold voltage slope or swing (SS)—to characterize how long it takes for the conductive channel region to form in a field effect transistor. In general, the quicker the channel region forms, the better, as that reflects a faster switching time. FIG. 1D reflects modeling results of the sub-threshold voltage slopes for the two illustrative TFET devices 10P, 10L described above (wherein EOT=0.8 nm; Ns=1020 cm−3; WF=4.05 eV; and Vds=1V). In general, the line-tunneling device 10L exhibits better switching time and a steeper SS slope than does the point-tunneling device 10P.
FIG. 1E depicts another form of field effect transistor—a vertically oriented, N-type, nanowire TFET device 30. In general, the device 30 includes a P-doped source region 34, an N-doped drain region 32 and a channel or intrinsic region 36. The channel region 36 is typically un-doped. Also depicted are a gate insulation layer 38 and a gate electrode 40. For a nanowire device like device 10P, the gate electrode 40 is positioned around the channel region 36. In some such devices, the gate electrode 40 is sized so as to overhang the source region 34 by a significant amount so as to induce line tunneling currents, as described above with respect to the device 10L.
What is needed is a TFET device that may exhibit better SS characteristics than those exhibited by the line-tunneling TFETs described above and a TFET device that is expected to produce acceptable drive current levels. Moreover, there is a need for such a TFET device that may be fabricated in a production environment where integrated circuit products are manufactured using mass production techniques.